Posted: October 1st, 2021

System verilog create a test plan and self-checking test-bench for


1. Reset which resets C to 0.

2. 4-bit signed inputs, A and B

3. 5-bit registered signed output C

4. 4 op-codes

a) add

b) sub

c) bitwise invert input A 

d) reduction OR input B

5. Assume the following encoding of the opcodes.


Opcode                               Encoding

add                                          2’b00

sub                                           2’b01

bitwise invert input A                2’b10

reduction OR input B                2’b11

You must use VCS and your testbench must be self checking. Cut and paste the transcript window into your HW submission. 


1. Test plan for ALU

2. Code for ALU testbench

3. Copy of transcript on terminal window after running VCS

4. Waveforms as observed using DVE. 

This testbench code and test plan fro ALU should be done using  with all the //comments in the code neatly explained why the step or code is there and the ALU_4_BIT.V  file is provide to use the design code of the ALU in the EDAPLAYGROUND. Use the ALU design and write a code according to the designed ALU.  THE ALU BIT FILE  can be opened in the EDAPLAYGROUND.COM itself.

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